Senior RTL/ASIC Design Engineer for Space-grade Silicon

SpaceX in Austin, TX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop next‑generation ASICs for Starlink and space infrastructure. You will define micro-architecture, write RTL in Verilog/System Verilog, and work with verification, timing, and physical teams to deliver fully verified designs on schedule, facing challenging clock domains and power optimization. This role requires strong collaboration and hands-on debugging, with extended hours for mission-critical deadlines.