Lead Front-End SoC Design Engineer (PCIe/Ethernet)

Astera Labs is seeking a Principal Digital Design Engineer in the United States to lead front-end circuit design, RTL, and verification for high‑performance network controllers. You will own architecture‑to‑GDSII delivery and work with teams to meet tight timing on advanced CMOS processes. The role requires hands‑on experience with PCIe, ULink, Esun, Ethernet, and strong front‑end design, verification, and test expertise. UVM familiarity and US work authorization are preferred.