Design Verification Engineer

We are seeking a Senior Formal Verification Engineer with 8–10+ years of experience in semiconductor design verification and a strong focus on formal verification methodologies. The ideal candidate will have hands-on experience with Synopsys VC Formal and/or Cadence JasperGold, strong expertise in SystemVerilog Assertions (SVA) and formal property specification, and experience with FPV, connectivity checking, register verification, equivalence checking, and coverage analysis. The candidate should also be proficient in SystemVerilog, UVM, and scripting languages such as TCL, Python, or Perl for verification flow automation.