ASIC Physical Design Engineer II: RTL-to-GDSII Specialist

Cisco’s Silicon One team is seeking a Physical Design Engineer to lead RTL-to-GDSII implementation for cutting-edge Networking chips. You will optimize floor planning, timing, and backend flows while collaborating across RTL, DFT, and EDA teams to secure high-performance silicon. The role requires expertise in ASIC physical design concepts, floor planning, clock and power distribution, and STA. Proficiency with Cadence Innovus, Synopsys tools, and scripting is highly valued.