Lead SerDes Bring-Up & Validation Engineer

L6

jobleadsusSan Jose, CAyesterday
Astera Labs, based in San Jose, CA, seeks a Principal SerDes Bring-up Validation Engineer to lead end-to-end post-silicon bring-up, validation, and characterization for high-speed PHYs. You will build automation, collaborate across AMS design, firmware, and system teams, and drive data-driven optimization of performance and reliability. You will design and execute bring-up plans, develop test objectives and pass/fail criteria, and mentor across disciplines to accelerate time-to-data and improve
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Level

LeadL6

Location

San Jose, CA

Occupation

Computer Hardware Engineers

Industry

Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)

Posted

yesterday

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