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Sr Principal Mixed Signal Verification Engineer

L6

peyton resource groupRichardson, TXyesterday

Occupations

Electronics Engineers, Except ComputerElectrical EngineersValidation Engineers

Industries

Semiconductor and Related Device ManufacturingResearch and Development in the Physical, Engineering, and Life SciencesOther Electronic Component Manufacturing
Senior Principal Mixed-Signal Verification Engineer
Experience: Senior-level, 15+ years
Position Summary: Lead top-level design verification for mixed-signal and power-management ICs, ensuring functional accuracy, performance, and manufacturability across diverse applications.
Key Responsibilities: Develop and execute metric-driven verification plans based on functional, performance, and test specifications. Create constrained-random tests, automated checkers, and coverage models within UVM environments. Develop accurate RNM and Verilog-AMS models for top-level simulations. Verify power-management ICs, including motor drivers, battery management, DC-DC regulators, and power-loss protection. Collaborate with design and test teams to debug issues and improve first-pass silicon success. Automate verification processes and continuously improve methodologies. Support customer-facing technical discussions and use-case-driven verification.
Required Qualifications: Bachelor’s degree in Electrical Engineering or a related field.
15+ years of experience in analog/mixed-signal design verification or power-management IC development, or equivalent education and experience. Strong expertise in UVM, test development, functional coverage, and global checkers. In-depth knowledge of analog and power-management circuits, including LDOs, amplifiers, bandgaps, DC-DC regulators, oscillators, and asynchronous state machines. Experience with SPICE/Spectre, event-based simulators, mixed-signal co-simulation, and simulation and silicon debugging. Excellent analytical, problem-solving, communication, and collaboration skills.
Preferred Qualifications: Master’s degree in Electrical Engineering or a related field.
Experience with top-down design and verification methodologies. Proficiency in Python or shell scripting. Familiarity with SV-UDN/EENET modeling, SystemVerilog assertions, and functional coverage. Experience with GUI-based and command-line simulation workflows. Understanding of AI integration into verification workflows.
Travel: Up to 10% domestic or international travel.
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Apply now (opens in a new tab)

Level

LeadL6

Location

Richardson, TX

Occupation

Electronics Engineers, Except Computer

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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