Senior Digital Design Lead – PCIe/CXL ASICs

Astera Labs in San Jose, CA, is seeking a Senior Manager/Manager, Digital Design, to lead front-end digital design for high‑performance PCIe & CXL devices, guiding RTL development, verification, physical design, tape-out, and product shipment. This role offers the chance to influence the development of purpose-built connectivity products for AI infrastructure and to establish scalable design practices while delivering silicon that advances next-generation AI systems.