Lead Design Verification Engineer: SystemVerilog/UVM & DDR6

Renesas Plano is seeking a Principal Design Verification Engineer to provide technical leadership for verification of next‑generation memory interface products, including data buffer silicon. You will drive verification strategy and execution for complex digital designs, collaborating with design teams to ensure functionality and performance meet requirements. The ideal candidate has deep semiconductor verification expertise with System Verilog and UVM, and experience guiding verification plans