Senior SoC Physical Design Engineer: Power & Signoff

Qualcomm Technologies, Inc. is seeking a professional to independently plan and execute physical design flows for high-speed DDR, graphics, and SOC blocks with a focus on power efficiency and performance. The role covers Floor Planning, Clock Tree Synthesis, Place and Route, PDN, timing analysis, and verification checks (LVS/DRC). You will support tapeout signoff and participate in design reviews and cross-functional meetings.