RTL Design Engineer: NoC & Interconnect

Architect Labs is seeking a seasoned RTL Design Engineer to own the AI-driven interconnect fabric for production silicon. You will define block-level microarchitecture, drive high-speed NoC design, and implement AMBA-based interconnects, ensuring low latency and high bandwidth for ML workloads. Collaboration with DV, SW and ML teams is essential for a successful tapeout. You will lead crossbar and NoC topology design, work on PCIe/CXL/UCIe bridges, and support FPGA prototyping on Xilinx