Senior Design Verification Engineer

Responsibilities: Closely work with designers and architect to come up with verification and execution plans Influence and drive verification environment architecture with a team of engineers Participate in verification of a complex IP block, take ownership of some of the key features Work on test plans, test case development, regression and coverage closure Guide and mentor junior engineers as required Desire and enthusiasm to grow into leadership role taking progressive responsibility over time

Qualifications: At least 5 years of experience focused on IP and/or SOC verification with successful completion of multiple ASICs that are in production Ability to understand existing verification infrastructure, and execute projects based on those, at the same time influence improvements in existing flows/infrastructure Solid understanding of System Verilog constructs, UVM, and C++ is required Experience writing scripts in Perl or Python, good knowledge in Makefile is a plus Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification Good understanding of code and functional coverage, ability to influence coverage improvement with design and verification teams Experience and ability to influence regression management tools and processes Knowledge of or experience with advanced processor architectures (CPU, GPU, NPU/AI accelerators) and their verification methodologies is a strong plus.