Remote FPGA Compiler Architect: QoR & Timing Optimization
alteraSan Jose, CA
$232,000 - $305,000 per year
Apply nowRemote FPGA Compiler Architect: QoR & Timing Optimization
L6
alteraSan Jose, CAyesterday
$232,000 - $305,000 per year
Occupations
Computer Hardware EngineersElectronics Engineers, Except ComputerComputer Systems Engineers/ArchitectsIndustries
Semiconductor and Related Device ManufacturingElectronic Computer ManufacturingOther Electronic Component ManufacturingAltera Corporation in San Jose, CA seeks a Senior Principal Engineer to shape the FPGA software platform, leading architectural decisions and optimization innovations for timing closure, area and power.
You will influence long-term technology directions across synthesis, placement, routing, and physical optimization, collaborating with product teams and customers to translate market needs into differentiating solutions.
Apply now
Level
LeadL6
Salary
$232,000 - $305,000 per year
Location
San Jose, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
yesterday
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