Senior NoC/SoC ASIC Design Engineer - Verilog & Python

Wipro Limited in Mountain View, California, is seeking an experienced Senior ASIC / SoC NoC Design Engineer or Senior ASIC Design Engineer to drive high-performance NoC IP within AI SoCs. The role requires hands-on RTL design, microarchitecture, and strong collaboration across architecting and verification teams. The position emphasizes Synthesis, timing, CDC/Lint, PPA trade-offs, and post-silicon support, with Python scripting to automate design flows.