Senior ASIC Design Engineer - RTL & Timing Expert

Cisco Systems, Inc. in the United States seeks an experienced ASIC Design professional to drive micro-architecture and Verilog RTL implementations, collaborating across verification and physical design to meet timing, power, and performance goals. Join the Common Hardware Group to contribute to Silicon One and other platforms powering Cisco’s AI-era hardware. A strong RTL background and relevant degrees are required, with full tapeout experience preferred.