RTL-to-GDSII Physical Design Engineer - Tapeout Ready
tekclapSan Jose, CA
RTL-to-GDSII Physical Design Engineer - Tapeout Ready
L6
tekclapSan Jose, CAtoday
Industries
Semiconductor and Related Device ManufacturingPrinted Circuit Assembly (Electronic Assembly) ManufacturingOther Electronic Component ManufacturingTekClap in San Jose, CA is seeking highly skilled Physical Design Engineers with hands-on RTL-to-GDSII implementation experience for advanced-node ASIC/SoC designs.
Responsibilities include:
RTL-to-GDSII flow, CTS, routing, and timing closure, along with physical verification and ECO-driven optimization to meet PPA targets. You will collaborate with cross-functional teams to ensure successful tapeouts.
Apply now
Level
LeadL6
Location
San Jose, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
today
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