Senior ASIC Verification Engineer

Key responsibilities: Implement SSN-based test flow DFT architectures using Siemens Tessent tools for RTL and gate netlist DFT implementation Generate ATPG test patterns and drive scan-based diagnosis methodology for silicon failure debug Evaluate design readiness for scan insertion and integrate DFT fabrics within subsystems to ensure correct functionality and test coverage

Required qualifications: Bachelor's degree with 8 years, Master's with 6 years, or PhD with 3 years of related experience Prior experience with ASICs, including DFT setup, integration, and validation Experience implementing DFT architectures, including scan insertion and memory/logic BIST Strong RTL experience to debug DFT-related issues Familiarity with Verilog/SystemVerilog and advanced silicon process nodes for high-speed designs