Senior VLSI Design Engineer - Timing & ASIC Expert

Broadcom in Fort Collins, CO is seeking a senior engineer with deep VLSI/ASIC design and timing analysis expertise to tackle complex development and support challenges across global teams. You will apply static timing analysis tools (PrimeTime, Cadence Tempus), model RC networks, and develop timing constraints while collaborating with engineers across time zones. Strong TCL and scripting skills are required.