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ASIC Design Engineer, Cloud TPU

L6

googleSunnyvale, TXtoday
Overview: In this role you will shape the microarchitecture and RTL for Google's TPU On-Chip Network, partnering with verification and physical design to meet timing, area, and power goals. You’ll lead power optimization initiatives across on‑chip networks and support post‑silicon validation and debugging. You’ll drive design-tool and flow enhancements and collaborate across firmware, validation, and DV/PD teams to deliver cutting‑edge AI accelerators. Compensation / Benefits bonus target equity benefits
Responsibilities: Define and document TPU microarchitecture and RTL blocks Collaborate with Verification to develop test plans and debug RTL Work with Physical Design to meet timing, area, power, and manufacturability targets Lead power optimization and automation initiatives for on‑chip-network components Support post‑silicon validation and hardware debugging Lead development and enhancement of internal design tools, flows, and methodologies Contribute to integration efforts of digital logic within TPU architecture Own critical design deliverables and drive design methodology improvements
Key requirements: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; or equivalent practical experience 8 years of RTL design experience Experience in digital design and microarchitecture design Experience optimizing for performance, power, and area Cross‑functional experience with DV and PD teams Collaborative and cross-functional teamwork Strong problem-solving and debugging mindset Effective communication of technical concepts across teams RTL design and microarchitecture Power optimization experience Experience with power analysis tools like PowerArtist and PTPX
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Level

LeadL6

Location

Sunnyvale, TX

Occupation

Computer Hardware Engineers

Industry

Computer Systems Design Services

Posted

today

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