Design Verification Engineer

🚀 Multiple Design Verification (DV) Opportunities - U.S. Based (Hybrid & Onsite) 🚀We are partnered with several cutting-edge semiconductor clients who are actively hiring Design Verification Engineers across a range of domains. These roles are NOT fully remote - each has a defined hybrid or onsite expectation, outlined belowIf you’re a DV engineer exploring your next move, chances are one of these aligns well👇🔹 Bay Area, CA – Onsite (4x/week)DV Engineer – AI Native • Deep experience verifying AI/ML accelerators, LLMs, TPUs, etc. • 2–13 years of experience🔹 Bay Area, CA – HybridDV Engineers – Multiple DomainsLooking for DV engineers with experience in one or more of the following: • CPU / Processor • Networking • PCIe / Ethernet • AI Accelerators • UCIe / CXL • NoC / NIC • Memory Controller