Tech Lead: Power Integrity & IR/EM for SoCs
astera labsSan Jose, CA
Tech Lead: Power Integrity & IR/EM for SoCs
L6
astera labsSan Jose, CAtoday
Occupations
Computer Hardware EngineersElectronics Engineers, Except ComputerInformation Technology Project ManagersIndustries
Semiconductor and Related Device ManufacturingResearch and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)Electronic Computer ManufacturingAstera Labs is scaling the connectivity fabric behind the world’s largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship. As a Technical Lead Physical Design Engineer- Power Integrity, you will own IR drop and EMIR analysis and closure across Astera Labs' connectivity ASIC portfolio, driving power integrity from early floorplan through tapeout.
You will partner closely with power grid, floorplan, package, and implementation teams to ensure stable power delivery,
Apply now
Level
LeadL6
Location
San Jose, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
today
To get sharper similar jobs, create your profile using the link below.