Senior Physical Design Engineer for High-Performance ASICs

Tachyum in Las Vegas seeks a senior IC design engineer to drive ultra-high performance, low-power data-processing chips. You will work with RTL teams to meet aggressive PPA targets and contribute to floorplanning, timing closure, and clock-tree design. The role requires 5+ years in semiconductor design, Verilog expertise, and experience with Innovus. Strong collaboration skills and willingness to mentor junior engineers are essential.