Lead Power Packaging Engineer – SiP & Wafer-Level Tech

L7

renesas electronicsPhoenix, AZyesterday

$180,000 - $240,000 per year

Renesas Electronics Corp. is seeking a senior Package Technology Development leader to drive R&D and NPI for AI/Datacenter infrastructure power packaging. You will manage OSAT/CM collaborations, define roadmaps, and optimize processes to meet stringent product qualifications. The role requires 15 to 20 years in package development with emphasis on power SiP/module and wafer-level/flip-chip packaging, plus strong analytical and presentation skills.
Apply now
Apply now

Level

ManagerL7

Salary

$180,000 - $240,000 per year

Location

Phoenix, AZ

Occupation

Electronics Engineers, Except Computer

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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