Senior Physical Design Engineer — FPGA & SoC Innovation

Altera Corporation in San Jose, CA, invites a Senior Physical Design Engineer to lead physical implementation of IP and SoC designs from RTL to GDSII, driving timing closure, power optimization, and signoff for next-generation FPGA products. You will collaborate with RTL, DFT, timing, and CAD teams to deliver high-quality silicon, apply advanced PPA techniques, and continuously improve design flows and automation.