Senior Principal DFT Architect – SoC Test & Verification

Cadence Design Systems is seeking a highly motivated hardware engineer to join the Modus R&D team in the Design-For-Test (DFT) IP unit. You will design and implement DFT hardware, test fabrics, and on‑chip test networks for next‑generation SoCs, including LBIST, MBIST, POST and IST capabilities. You will collaborate across RTL, verification, synthesis, and physical design teams to ensure high‑coverage, low‑cost test strategies while delivering reusable IP and robust test infrastructure.