Senior ASIC Formal Verification Engineer

Etched seeks a Formal Verification Engineer to advance verification across ASIC DV, interface IP, and SoC subsystems powering our ASICs. You will drive formal properties, enable proof convergence, and collaborate with architects, RTL designers, DV, emulation, software and firmware teams to prove design correctness and minimize corner-case bugs. Expect to build reusable formal environments, employ SystemVerilog Assertions, and align verification with simulation and regression.