Senior Digital Design Lead – PCIe/SoC Frontend

L6

astera labsSan Jose, CA2 days ago
Astera Labs seeks a Senior Digital Design Engineer in the United States to develop micro-architecture and front-end circuit design, including RTL, synthesis, and IP integration for high-performance network controllers. The role requires strong knowledge of PCI-Express, Ethernet, and related protocols, with hands-on experience in verification, bring-up, and debug across complex SoC blocks.
Apply now
Apply now

Level

LeadL6

Location

San Jose, CA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

2 days ago

To get sharper similar jobs, create your profile using the link below.

Create profile