Staff RTL Design Engineer

Responsibilities: Own and be responsible for pre-tape out quality for digital SOC modules on the MCU. Explore architecture and develop micro-architecture. RTL development for IPs and SOCs using Verilog. Identify, select, and integrate 3rd party IPs. Collaborate with verification and FPGA teams in test plan development and debugging. Work with the Physical Design team to meet timing and power targets. Assist in silicon bring-up and validation. Run quality check tools (LINT, CDC, RDC) and address issues.

Requirements: Bachelor’s degree in Electronics Engineering, Electrical Engineering, Instrumentation & Control Engineering, or a related field, plus 5-8 years of experience. Deep and broad knowledge of current and emerging SOC design technologies. Expertise in designing, implementing, and troubleshooting IPs and SOCs. Understanding of customer needs and the competitive landscape. Ability to estimate impact, plan, lead implementations, and positively influence the output. Capability to architect and guide programs across various technical areas. Seniority level Mid-Senior level Employment type Full-time Job function Semiconductor Manufacturing