SoC Physical Design Methodology Engineer
appleSan Jose, CA
SoC Physical Design Methodology Engineer
L6
Industries
Semiconductor and Related Device ManufacturingResearch and Development in the Physical, Engineering, and Life SciencesOther Electronic Component ManufacturingOverview:
Join Apple’s Hardware team to shape the physical design methodology that delivers optimal power, performance, and area for SoCs. You will collaborate across multi-functional groups to drive robust, efficient flows from theory to silicon and to quantify silicon measurements against models. Your work will focus on mitigating PPA degradation, improving interconnects, and applying data science techniques when beneficial. This role offers impact on next-generation Apple products and requires hands-on engineering with a strong systems perspective. You’ll be at the heart of design verification and flow development that scales with industry-leading technology. Compensation / Benefits Comprehensive medical and dental coverage Retirement benefits Apple stock programs Tuition reimbursement Relocation eligibility Discretionary bonuses or commissions
Responsibilities:
Develop and implement physical design methodologies to improve PPA of on-chip interconnects Perform electrical analysis to understand physical effects on performance Create strategies to mitigate PPA degradation seen in silicon Run signoff flows and compare against silicon measurements Collaborate with standard cell team to identify cells improving PPA, yield, or productivity Work with CAD and design teams to update production design flows Verify theories by planning silicon verification Apply data science and machine learning to methodology development
Key requirements:
10+ years of relevant industry experience At least 5 years of physical design experience on SoC designs Experience with advanced technology nodes Knowledge of interconnects, parasitic extraction, and manufacturing effects on non-idealities Deep understanding of power delivery and how noise impacts chip performance Inductance effects and circuit design experience Proficiency with Spice simulations Familiarity with static timing analysis tools and methodologies Proficient in Python and Tcl scripting Experience with flow development for large user bases on tight schedules Strong intellectual curiosity Excellent communication skills Organized, self-starter, adaptable Parasitic extraction Power delivery and supply noise analysis Interconnect modeling
Apply now (opens in a new tab)
Level
LeadL6
Location
San Jose, CA
Occupation
Electronics Engineers, Except Computer
Industry
Semiconductor and Related Device Manufacturing
Posted
today
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