Senior Memory Architect: High-Speed, Low-Power RAM Design

L6

lattice semiconductorSan Jose, CAtoday
Lattice Semiconductor, with a major presence in San Jose, California, seeks a Sr. Memory Designer to lead the design of high-speed, low-power memory blocks for FPGA architectures. You will own memory architecture, verification, and integration across the full design flow, collaborating with architecture and design teams to meet performance and yield targets. You will contribute to next-generation memory solutions, drive optimization, and ensure robust design practices while working in a
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Level

LeadL6

Location

San Jose, CA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

today

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