Lead Physical Design Engineers

Analyze the design and divide into small blocks. Split the circuit such that the number of connections between partitions is minimized. Based on the design analysis identifying appropriate place for different blocks within the chip area. Allocating places for external Hard IPs. Placing and optimizing the various small blocks identified during partitioning process: Post Placement Optimization (PPO) before clock tree synthesis (CTS) Routing the various clock signals within the design so that the clock skews are optimized: Clock Tree Synthesis (CTS) Perform the STA, across the complete design to ensure that all the timing checks are clean: Constraint Generation Budgeting Timing Sign off, IR/EM Analysis Signal integrity Perform Physical Verification against various critical parameters & criteria: Layout Vs Schematic Checks (LVS) Design Rule Checks (DRC) Electrical Rule Checks (ERC)