Senior SoC RTL Design Engineer - Edge AI ASIC

A tech company specializing in semiconductor solutions is hiring a Senior SoC RTL Design Engineer in San Jose, California. The role involves leading RTL development and ensuring smooth integration of subsystems and IP components. Candidates should have over 7 years of experience in RTL design and integration, particularly with SystemVerilog. Benefits include equity, comprehensive insurance, PTO, and relocation assistance. This position offers the opportunity to work on innovative semiconductor technologies and collaborate with multidisciplinary teams.