Lead Post-Silicon DVT Engineer for High-Speed ASICs

celero communicationsIrvine, CAyesterday

Occupations

Computer Hardware Engineers Validation Engineers Electronics Engineers, Except Computer

Industries

Semiconductor and Related Device Manufacturing Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)Semiconductor Machinery Manufacturing

Celero Communications, Inc. is seeking a Principal Design Validation & Test (DVT) Engineer in Irvine, CA to spearhead post-silicon validation for next-generation coherent DSP ASICs enabling AI and hyperscale networking. You will drive silicon characterization, enable first silicon bring-up, and build validation infrastructure while collaborating across Architecture, RTL, Firmware, Systems, and Customer Engineering. Strong leadership and a strategic validation mindset are required.

Apply now

Level

LeadL6

Location

Irvine, CA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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