Senior Physical Design Engineer - Low-Power SoC

Innophase IoT in California is seeking a Physical Design Principal Engineer to own the entire RTL-to-GDS flow for a low-power SOC, including floorplanning, place&route, CTS, STA, and signoff. You’ll join a team delivering advanced wireless semiconductor platforms in a fabless environment. The role requires 10+ years in physical design or 15+ years with a bachelor’s, and strong Cadence tool experience. Located in San Diego or San Jose, CA for on-site collaboration and execution.