Analog Intern: DDR PMIC Architecture & Cadence Design

Renesas Electronics invites an Analog Intern for Summer 2027 to contribute to the development of the next generation DDR PMIC. The role focuses on researching PMIC control architectures, with guidance from Design and Applications engineers, performing simulations, and building Cadence-based circuits. Ideal candidates are PhD or Master students who have not graduated before September 2027, with strong Power Electronics and Analog design backgrounds and familiarity with SIMPLIS and Cadence.