Lead ASIC RTL Design Engineer

Lead ASIC RTL Design Engineer — Remote (U.S.) - No visa sponsorship

Define microarchitecture for complex subsystems and document design specifications Implement high-quality, reusable RTL in System Verilog with clear interface definitions and design intent Incorporate assertions and design-for-debug features within RTL Design Ownership & Implementation Lead front-end design activities including linting, clock/reset domain analysis, and synthesis readiness Collaborate with physical design teams on floor planning, timing closure, and implementation tradeoffs Take responsibility for achieving performance, power, and area (PPA) targets for assigned blocks High-Speed Interfaces & Memory Systems Design and integrate high-bandwidth interfaces and interconnects (e.g., AMBA-based protocols, coherent fabrics) Work on memory subsystem integration, including external DRAM and high-throughput memory solutions Coordinate with internal teams and third-party IP providers to ensure proper integration and functionality Engineering Processes & Tooling Establish and maintain RTL design standards, reusable components, and signoff criteria Contribute to automation and workflow improvements using scripting and build systems (Python, Tcl, CI pipelines) Collaboration & System Integration Partner with verification teams on test planning, coverage goals, and model alignment Work with architecture and performance engineering to validate design intent against system-level expectations Support silicon bring-up, debugging, and downstream customer or system integration efforts Technical Leadership Mentor less experienced engineers and provide guidance on design best practices Lead design reviews and help drive key technical decisions across teams Advocate for scalable, efficient, and high-quality engineering solutions