Senior ASIC Physical Design Architect | Low-Power &

Micron Technology is seeking a seasoned ASIC Engineer to lead block-level and full-chip physical design, including floorplanning, placement, CTS, routing, and tape-out for DRAM tester solutions. You will drive timing closure across modes and corners, ensure power integrity, and support signoff through IR/EM analyses on advanced nodes. The role emphasizes developing efficient APR flows and automation, owning closure work, and coordinating with cross-functional teams for successful tape-out across