ASIC Physical Design Engineer II — RTL-to-GDSII Expert

Cisco Systems, Inc is seeking a Physical Design Engineer to lead RTL-to-GDSII implementation for advanced nodes and collaborate across RTL, DFT, and EDA teams. You will drive floor planning, place-and-route, clock/power distribution, and timing convergence to deliver high-performance networking chips. Ideal candidates have hands-on experience with STA, timing closure, and scripting for automation, plus familiarity with Cadence Innovus, Synopsys ICC2, and Design Compiler.