Senior Physical Design Engineer: PnR, PPA, Timing Closure

Wipro Limited in Austin, Texas is seeking a Physical Design Engineer with strong PnR, PPA optimization, and timing convergence to drive block-level design from netlist to GDSII. You will perform floorplanning, CTS, routing, and timing closure across advanced nodes, collaborating with RTL/STA/Signoff teams to tape out complex silicon. The role requires 8–10 years in VLSI physical design, expertise with Fusion Compiler/ICC2 and Prime Time, and hands-on PPA and EMIR analysis.