Top-Level SoC Physical Design Engineer

Apple Inc. in Seattle seeks a senior chip design lead responsible for implementing complete chip design from netlist to tapeout. You will work with FE and physical design teams to drive architecture, timing, and physical convergence, across multi-domain environments. The role requires a BS with 10+ years in ASIC/SoC design, familiarity with floorplanning, clock/power distribution, and IP integration, and you will influence layout decisions and verification flows. Base salary range shown applies.