RISC-V Physical Design Engineer — PPA & Signoff Specialist

ACL Digital is seeking a seasoned Physical Design Engineer to lead the implementation of high-performance RISC-V based processor designs from RTL to GDSII. You will own full-chip and block-level physical implementation, timing closure, power optimization, PPA, and sign-off across domains. Ideal candidates have 8+ years of block-level PD experience, with hands-on work on EM/IR, power grids, floorplanning, clock-tree synthesis, and sign-off readiness using industry tools.