FPGA Soft CPU Architect – RISC-V/Nios V
jobleadsusSan Jose, CA
FPGA Soft CPU Architect – RISC-V/Nios V
L6
jobleadsusSan Jose, CAyesterday
Industries
Semiconductor and Related Device ManufacturingElectronic Computer ManufacturingComputer Systems Design ServicesAltera is seeking an innovative Soft CPU Design Engineer to join its IP Engineering team at the San Jose, CA headquarters. You will design and optimize Soft CPU cores tailored for Altera FPGA architectures, focusing on high performance and area efficiency.
Responsibilities include:
RTL design in SystemVerilog, PPA optimization, timing closure, configurable ISA extensions, and collaboration with DV teams on simulations and hardware validation.
Apply now
Level
LeadL6
Location
San Jose, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
yesterday
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