RISC-V Post-Silicon Validation Engineer

L6

tenstorrent universitySanta Clara, CAtoday
Tenstorrent is seeking a Post‑Silicon Validation Engineer to drive bring‑up, validation, and debugging of RISC‑V based SoCs. The role sits at the intersection of silicon, firmware, and system software, requiring hands‑on lab experience and deep understanding of SoC architectures. The position is hybrid, based out of Austin TX or Santa Clara CA, with opportunities at various experience levels and compensation aligned with the level and location.
Apply now
Apply now

Level

LeadL6

Location

Santa Clara, CA

Occupation

Validation Engineers

Industry

Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)

Posted

today

To get sharper similar jobs, create your profile using the link below.

Create profile