Senior Physical Design Engineer - 3nm & Low Power

L6

ina solutionSan Jose, CAyesterday
INA Solution is seeking a highly skilled Physical Design Engineer with 10-20 years of experience to join their team in San Jose, California. The ideal candidate will have expertise in RTL2GDS flow and design tapeouts in advanced process technology, along with proficiency in Synopsys EDA tools. This role emphasizes low-power implementation techniques, clock tree synthesis, and power gating. Candidates should be familiar with PTPX power flow and have a solid background in various power management techniques.
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Level

LeadL6

Location

San Jose, CA

Occupation

Electronics Engineers, Except Computer

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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