Senior Physical Design Engineer, SoC & PnR Expert

Fortell in California is seeking an experienced ASIC Physical Design Engineer to drive chip implementation from synthesis through signoff, partnering with architects, RTL designers, and DFT engineers. You will ensure power-aware convergence, meet strict schedules, and lead verification signoffs across partitions. This role requires 7+ years in physical design, fluency with Innovus/Tempus/Quantus, and strong TCL scripting to optimize flows and reduce risk across SoC implementations.