Senior ASIC Design Engineer: Front-End & DFT

AMD in San Jose, CA, is seeking a candidate to join the front-end design/integration team to deliver high-quality silicon and achieve first-pass silicon success. You will implement and verify DFT architectures and features, including scan insertion and ATPG pattern generation. The ideal candidate will have strong communication and problem-solving skills, experience with DFT methodologies, and proficiency in Verilog RTL, scripting, and EDA tools.