ASIC Packaging SI/PI Engineer - High-Speed 56G SerDes

Cisco Systems, Inc. in San Jose, CA is seeking a Signal and Power Integrity Engineer to join the Cisco Silicon One team. You will design, verify, and optimize packaging for high-performance ASICs and collaborate closely with the layout and design teams, with a commute to the office required 4–5 days per week. Candidates should have a degree in electrical engineering with 4+ years for Bachelor's or 2+ years for Master’s and hands-on SI/PI, high-speed design, and industry tools.