RTL Design Engineer for TPU ASIC – AI Hardware

L6

googleSunnyvale, CAyesterday
Google Sunnyvale, CA, is seeking an experienced RTL design engineer to shape the future of AI/ML hardware acceleration. You will drive TPU architecture, design RTL IP for ASIC products, and collaborate with software and system hardware teams to bring complex digital designs from concept to production. The role focuses on SoC RTL design for data center accelerators, clocking and reset management, integration with software, and collaboration across multiple teams to deliver scalable AI solutions.
Apply now
Apply now

Level

LeadL6

Location

Sunnyvale, CA

Occupation

Computer Hardware Engineers

Industry

Electronic Computer Manufacturing

Posted

yesterday

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RTL Design Engineer for TPU ASIC – AI Hardware at google |...