Senior Physical Design Engineer - Frontier AI Chips

L6

consensusSan Jose, CAyesterday
Etched is building a new category of AI hardware; as the top-level PD engineer you will own full-chip implementation from floorplanning to GDSII, driving PPA optimization and timing closure. You will collaborate with RTL designers to iterate rapidly and ensure successful tapeouts. Lead clocking across all corners, manage top-level timing closure, and own PV at block and full-chip levels. Strong Cadence/Synopsys flows and scripting proficiency are essential for success in our fast-paced,
Apply now
Apply now

Level

LeadL6

Location

San Jose, CA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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