Design Verification Lead - SerDes/PHY IP

Astera Labs is seeking a Principal Design Verification Engineer to own the functional verification of high-speed SerDes/PHY IP. You will architect verification environments, drive coverage, and ensure first-pass silicon success on the analog/digital boundary for next-generation AI systems. You will collaborate with PHY analog/mixed-signal designers, digital architects, and SoC teams to verify multi-Gbps SerDes blocks that power leading AI platforms, including UALink, UCIe, PCIe Gen 6/7, and