Hardware Design Engineer 1
tpi global formerly tech providersSanta Clara, CA
Hardware Design Engineer 1
L6
tpi global formerly tech providersSanta Clara, CAtoday
Industries
Semiconductor and Related Device ManufacturingOther Electronic Component ManufacturingComputer Systems Design ServicesJob Description:
SENIOR SILICON DESIGN ENGINEER THE ROLE:This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical VerificationTHE PERSON:Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teamsRESPONSIBILTIES:This engineer will work on leading edge technology nodes designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floor planning, establishing design methodology, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
PREFERRED SKILLED SETS:Major in EE, CS or related, master s degree with 3+ years or Bachelor with 5+ years working experience, preferably with high designs or other high-performance IP designs.
Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications. Mainly in ICC2, fusion compiler, calibre and Prime Time.
Experience in automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applicationsEDUCATION:Major in EE, CS or related, master s degree preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs.
Custom Fields: Name: Is this a returning FTE or Contractor (re-engage)?Value: NoneName: Work Site TypeValue: Onsite/HybridName: Is travel required for this position?
Value: NoName: Please indicate the exact site or location
Value: NoneName: Time Occasional
Value: NoName: Is this an Engineering or IT related position?
Value: YesName: Is this position related to Veriscale?
Value: No Meet Your Recruiter
Shiv Shekhar
Apply now (opens in a new tab)
Level
LeadL6
Location
Santa Clara, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
today
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